Patent attributes
One embodiment of the present invention provides a system that uses a single built-in-self-test (BIST) engine to test multiple on-chip memory structures. During chip-test or power-on-self-test in the system, the BIST engine tests multiple on-chip memory structures which reside at different locations on the chip. During this testing process, the BIST engine performs at-speed data-parallel testing operations for the multiple on-chip memory structures. In doing so, the BIST engine communicates with the multiple on-chip memory structures through data paths which are used for other purposes during normal operation of the chip, but which are used for communications between the BIST engine and the multiple on-chip memory structures during the testing process.
