Patent attributes
A pad layout suitable for being applied on a metal interconnection structure of an integrated circuit chip is provided. The pad layout includes a first signal pad, a second signal pad, a first non-signal pad, a second non-signal pad, a first trace, a second trace, a first guard ring and a second guard ring. The second signal pad is located adjacent to the first signal pad. The first non-signal pad is located adjacent to the first signal pad. The second signal pad is located adjacent to the second signal pad. The first guard ring surrounds the first signal pad and is connected to the first non-signal pad through the first trace. The second guard ring surrounds the second signal pad and is connected to the second non-signal pad through the first trace.