US Patent 7365523 Scrambling of the current signature of an integrated circuit
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Patent abstract
A method and a circuit for scrambling the current signature of a load including at least one integrated circuit executing digital processings, including the step of, at least on the load ground side, combining a current absorbed by a first linear regulator with a current absorbed by at least one capacitive switched-mode circuit with one or several switched capacitances.
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US Patent 07365523 Scrambling of the current signature of an integrated circuit US Patent 7365523 Scrambling of the current signature of an integrated circuit
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Patent Number
0736552300
Patent Number
736552300
Edits on 28 Mar, 2023
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Patent Jurisdiction
Patent Number
073655230
Date of Patent
April 29, 2008
0Patent Application Number
113494180
Date Filed
February 7, 2006
0Official Website
Patent Primary Examiner
Edits on 23 Sep, 2022
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Patent Jurisdiction
Patent Number
073655230
Date of Patent
April 29, 2008
0Patent Application Number
113494180
Date Filed
February 7, 2006
0Official Website
Patent Primary Examiner
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US Patent 07365523 Scrambling of the current signature of an integrated circuit
Infobox
Is a
Patent jurisdiction
Patent number
07365523
Date of patent
April 29, 2008
Patent application number
11349418
Date Filed
February 7, 2006
Patent primary examiner
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