US Patent 7366012 Synchronous memory device with reduced power consumption

A synchronous non-volatile memory device that includes a circuit for performing operations on the memory device, a circuit for receiving a request of operation and operative information required for performing the operation in temporal succession, an activation circuit for activating the circuit in response to the request of operation, a circuit for enabling the execution of the operation in response to the operative information, and a deactivation circuit for deactivating the operations performing circuit in response to the completion of the operation.