US Patent 7369433 Semiconductor memory device

A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first and second cell arrays, one of four data levels L0, L1, L2 and L3 (where, L0<L1<L2<L3) being written into the information cell, reference level Lr (where, L0<Lr<L1) being written into the reference cell to used for detecting the data level of the information cell, and wherein the sense amplifier circuit detects a cell current difference between the information cell and the reference cell simultaneously selected from the first and second cell arrays.