US Patent 7372765 Power-gating system and method for integrated circuit devices

A power-gating system and method for integrated circuit devices wherein the minimization of “Standby” or “Sleep Mode” current is a design factor and wherein an output stage is coupled directly between a supply voltage level (VCC) and a reference voltage level (VSS). In a representative complementary metal oxide semiconductor (CMOS) implementation, the gate of the N-channel output transistor in the final inverter stage may be driven below VSS in Sleep Mode while, alternatively, the corresponding P-channel transistor can be driven above VCC. In Active Mode, the switching speed of the output stage is not impacted, and the preceding stage can be made smaller than that of the output stage.