US Patent 7376027 DRAM concurrent writing and sensing scheme

This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switching circuit controlled by the first and second GBLs and controllably coupling a predetermined power supply source to the first and second BLs, separately, wherein when the first and second GBLs are asserted during a write operation, the switching circuit couples only one of the first and second BLs to the predetermined voltage supply source.