Patent 7376199 was granted and assigned to Xilinx on May, 2008 by the United States Patent and Trademark Office.
An example embodiment is directed to an arrangement and method for phase-aligning digital data to be sent by transmit-data modules over respectively-situated serial links. A reference clock signal is communicatively coupled to each transmit-data module, each transmit-data module having a data driver and a clock circuit. At the serial links, each respective data driver sends digital data in response to a clock-output signal and a phase-adjusted clock-load signal that is used to load the data driver. The phase of the clock-load signal is adjusted relative to misalignment between the clock-load signal and the reference clock signal so that each data driver loads the digital data in a time-aligned manner for link transmission. The present invention is useful in applications involving programmable logic devices and other skew-susceptible parallel transmission arrangements.