US Patent 7376797 Cache memory system and method using reference bits

A cache memory system includes a cache memory having a plurality of entries associated with a plurality of information storage units. Each of the information storage units is configured to store part of the information stored in a main memory. Reference bit storage units store a use status of entry data for a certain period of time. A hit detection circuit is connected to the information storage units. The hit detection circuit generates a hit signal to each of the reference bit storage units when the entry data is determined to satisfy use conditions.