Patent attributes
Methods and apparatus are provided for TMOS devices, comprising multiple N-type source regions, electrically in parallel, located in multiple P-body regions separated by N-type JFET regions at a first surface. The gate overlies the body channel regions and the JFET region lying between the body regions. The JFET region communicates with an underlying drain region via an N-epi region. Ion implantation and heat treatment are used to tailor the net active doping concentration Nd in the JFET region of length Lacc and net active doping concentration Na in the P-body regions of length Lbody so that a charge balance relationship (Lbody*Na)=k1*(Lacc*Nd) between P-body and JFET regions is satisfied, where k1 is about 0.6≦k1≦1.4. The entire device can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region to the drain.
