US Patent 7380097 Apparatus and method for controlling address conversion buffer

A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a second memory area shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.