US Patent 7382019 Trench gate FETs with reduced gate to drain charge

A field effect transistor includes a trench extending into a semiconductor region. The trench has a gate dielectric lining the trench sidewalls and a gate electrode therein. A channel region in the semiconductor region extends along a sidewall of the trench. The gate dielectric has a non-uniform thickness such that a variation in thickness of the gate dielectric along at least a lower portion of the channel region is inversely dependent on a variation in doping concentration in the at least a lower portion of the channel region.