US Patent 7382117 Delay circuit and test apparatus using delay element and buffer

There is provided a delay circuit that delays an input signal to output the delayed signal. The delay circuit includes a first delay element operable to receive the input signal and delay the input signal to output the delayed signal, a buffer operable to receive the delay signal output from the first delay element and correct a dullness of a waveform of the delay signal generated from the first delay element to output the corrected signal, and a second delay element operable to receive the delay signal output from the buffer and delay the delay signal to output the delayed signal.