Patent attributes
A semiconductor storage device has a memory cell array composed of a plurality of arrayed memory cells, word lines, bit lines, a bit line charging and discharging circuit, and a readout section. Each memory cell has two storage regions in vicinity of opposite ends of a channel region, first and second input/output terminals, and a control terminal. The readout section reads information stored in one of the first and second storage regions of a memory cell based on a first output equivalent to an output current from the memory cell when a current is passed from the first input/output terminal to the second input/output terminal of the memory cell and a second output equivalent to an output current from the memory cell when a current is passed from the second input/output terminal to the first input/output terminal.
