US Patent 7385861 Synchronization circuit for DDR IO interface

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first strobe signal having an unknown phase in relation to a local clock signal when receiving data from a memory. The second circuit may be configured to synchronize the first strobe signal with the local clock signal by (i) generating one or more second strobe signals and (ii) inserting a predetermined cycle delay between the one or more second strobe signals and the local clock signal.