Patent attributes
The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.
