US Patent 7386750 Reduced bus turnaround time in a multiprocessor architecture

Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff. The method may also include bypassing data from recovery latches and instead receiving data from pipeline latches into core logic, the received data mirroring data driven onto the system bus.