Patent attributes
A latch circuit comprises eight MOS transistors in which a first pair of transistors are connected in series between a voltage supply node and ground and a second pair of transistors are connected in parallel to the first pair between the voltage supply node and ground. A fifth transistor is connected between the gates of the first pair and a node between the transistors of the second pair and a sixth transistor is connected between the gates of the second pair and a node between the transistors of the first pair. The seventh transistor is a write transistor connected between a data in line and the node between the first pair of transistors and the eighth transistor is a clear transistor connected between the node between the second pair of transistors and ground.
