US Patent 7391054 Semiconductor device and manufacturing method thereof

The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.