Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Daisuke Sonoda0
Toshiki Kaneko0
Date of Patent
June 24, 2008
0Patent Application Number
112147940
Date Filed
August 31, 2005
0Patent Primary Examiner
Patent abstract
A display device has C-MOS p-Si TFTs which enable high integration by reducing spaces for P-MOS TFTs and N-MOS TFTs in a driving circuit or the like thereof. A self-aligned C-MOS process is adopted, which uses a half tone mask as an exposure mask for manufacturing the C-MOS p-Si TFTs mounted on the display device. With the use of the half tone mask, the alignment or positioning at a bonding portion between a P-MOS portion and an N-MOS portion becomes unnecessary, and, hence, the number of photolithography steps can be reduced and high integration of C-MOS TFT circuits can be realized.
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