US Patent 7391237 Robust and economic solution for FPGA bitfile upgrade

A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.