Patent attributes
A semiconductor memory device is provided. The semiconductor memory device includes an active commander for generating an active command upon receiving a plurality of control signals, a first signal generator configured to receive the active command, and generate a first latch signal for latching information associated with activation of the active command, a second signal generator configured to receive the first latch signal and a chip selection signal, generate a word-line activation signal and activation-information signal when the first latch signal and the chip selection signal are simultaneously enabled, and a reset controller configured to receive a second latch signal, the word-line activation signal, and the activation-information signal, and control the first signal generator to reset the first latch signal using the received signals.
