US Patent 7394285 Circuit for driving bus

A bus driving circuit includes a majority voter unit for comparing the number of logic high level bits with the number of logic low level bits among a predetermined number of bits of data; a latch unit for latching a first output signal in response to the compared result; and a flip-flop unit for latching the predetermined number of bits of data in synchronization with the clock; and a selection unit for selecting one of the latched data of the flip-flop unit and an inverted output of the latched data of the flip-flop unit according to the first output signal.