US Patent 7404115 Self-synchronising bit error analyser and circuit

A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparatorwherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; andwherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.