Patent attributes
A transistor array panel comprises a substrate, a transparent electrode disposed on the substrate, a gate line disposed on the substrate, a gate insulating layer disposed on the transparent electrode and the gate line, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a first insulating layer having an uneven surface, the first insulating layer disposed on the data line and the drain electrode, and a reflective electrode disposed on the first insulating layer, the reflective electrode connected to the transparent electrode and the drain electrode, wherein at least a portion of the transparent electrode is exposed.