Patent attributes
In a PLL frequency synthesizer outputting signals with different frequencies: voltage-controlled oscillators output the signals and have the oscillation frequencies controlled according to control voltages; a first switch selects one of the signals; a frequency divider generates a frequency-divided signal of the selected signal by use of a changeable frequency-division ratio; a phase comparator generates the phase difference between the frequency-divided signal and a reference signal; a second switch selects one of paths connected to low-pass filters; each low-pass filter is provided for one of the voltage-controlled oscillators, has a changeable time constant, and converts the phase difference into one of the control voltages; and a controller cyclically controls the first and second switches and the frequency divider so that the voltage-controlled oscillators continuously output the signals, and changes the changeable time constant of each low-pass filter after all of the signals become stable.
