US Patent 7405956 Line layout structure of semiconductor memory devices

A line layout structure of semiconductor memory device comprises first metal wire lines forming a bit line coupled to a memory cell, second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section word line electrically coupled to the memory cell, and third metal wire lines disposed substantially parallel to the second metal wire lines and over the second metal wire lines, the third metal wire lines forming a first power line or signal line.