US Patent 7405980 Shared terminal memory interface

A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. An integrated circuit memory includes a random-access memory. The random-access memory includes a first terminal for receiving selection information. The random-access memory includes a second terminal for selectively (i) receiving a command, or (ii) receiving or transmitting data in accordance with the selection information received by the first terminal.