US Patent 7406121 Adaptive clock-less equalizer circuit

A system and method for equalizing a signal is provided. In one implementation, the method includes generating a partially equalized signal from an input signal based on a plurality of coefficients associated with a feed-forward equalizer (FFE); generating decoded bit values based on the partially equalized signal, the decoded bit values being an equalized output signal; measuring error in the partially equalized signal; and adjusting the coefficients associated with the feed-forward equalizer (FFE) based on the error measured in the partially equalized signal. Values of the coefficient are not used to adjust of the coefficients associated with the feed-forward equalizer (FFE).