US Patent 7406495 Adder structure with midcycle latch for power reduction

A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.