US Patent 7408418 Phase locked loop circuit having reduced lock time

A phase locked loop circuit comprising a phase detector having a first input for receiving a first frequency signal and an output, a first filter adapted to filter the output electric signal of the phase detector, a voltage controlled oscillator adapted to generate a second frequency signal in response to the output filtered signal of the phase detector. The phase detector has a second input for receiving the second frequency signal and is adapted to compare it with the first frequency signal. The circuit comprises means adapted to amplify the difference between an electric signal coupled with the output of the phase detector and a reference electric signal and a second filter adapted to receive the output electric signal of the amplification means and to send an output electric signal to the voltage controlled oscillator. The circuit comprises further means adapted to modify the value of the electric signal in input to the second filter to decrease the response time of the second filter.