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US Patent 7409612 Testing of integrated circuits
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Patent
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Date Filed
January 28, 2004
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Date of Patent
August 5, 2008
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Patent Application Number
10545121
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Patent Citations Received
US Patent 12123912 Reconfigurable JTAG architecture for implementation of programmable hardware security features in digital designs
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US Patent 11768238 Integrated circuit with reduced signaling interface
US Patent 11867756 Reduced signaling interface method and apparatus
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US Patent 11879941 Scan testing using scan frames with embedded commands
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
7409612
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Patent Primary Examiner
Cynthia Britt
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