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US Patent 7415584 Interleaving input sequences to memory

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Patent Citations Received
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US Patent 12014068 System and method for double data rate (DDR) chip-kill recovery
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US Patent 11843393 Method and apparatus for decoding with trapped-block management
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Patent Inventor Names
Peter J. W. Graumann0
Sean G. Gibb0
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Patent abstract

An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency.

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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=074155840
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US Patent 07415584 Interleaving input sequences to memory US Patent 7415584 Interleaving input sequences to memory

Infobox
Patent Number
074155840
Patent Number
74155840
Edits on 23 Sep, 2022
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Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
074155840
Date of Patent
August 19, 2008
0
Patent Application Number
108444860
Date Filed
May 13, 2004
0
Official Website
https://pdfpiw.uspto.gov/.piw?Docid=074155840
Patent Primary Examiner
‌
B. James Peikari
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=07415584
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 US Patent 07415584 Interleaving input sequences to memory

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
07415584
Date of patent
August 19, 2008
Patent application number
10844486
Date Filed
May 13, 2004
Patent primary examiner
‌
B. James Peikari

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