Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Yunteng Huang0
Date of Patent
August 26, 2008
0Patent Application Number
115502230
Date Filed
October 17, 2006
0Patent Citations Received
Patent Primary Examiner
Patent abstract
A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.
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