Patent attributes
A clock divider includes a first state storage unit, a second state storage unit a first control signal generating unit a state update unit and an output unit. The first state storage unit receives an update signal to perform transition of a first state value in synchronization with a clock signal. The second state storage unit performs transition of a second state value in synchronization with a first state signal corresponding to the first state value. The first control signal generating unit generates a first control signal for determining a first state transition path based on a first division ratio control signal. The state update unit generates the update signal based on the first control signal and the first state signal. The output unit selectively output the first state signal or a second state signal corresponding to the second state value.
