US Patent 7424638 Multipath processor with dedicated buses

A device includes a processor (1) having two states (111, 112) each storing a processing path, a central unit (11) processing the paths in those states, at least one transfer bus (13) between the processor and peripherals, at least one processing path backup and restore bus (14), distinct from the data bus, and a backup and restore memory (15). A processing path controller (16) controls the transfer of a processing path between the memory and a state while the processor processes the processing path of another state. This allows for a reduction in the time wasted by the controller on restore or backup transfers.