US Patent 7424694 Integrated circuit layout device, method thereof and program thereof

A layout device for an integrated circuit executes calculating a timing value with respect to each wiring path by a analysis based on connection information and delay information of wirings, determining a target value serving as an improvement target of the wiring path, detecting an error wiring path exhibiting the timing value larger than the target value, changing the wiring connection so that the error wiring path shows a timing value smaller than the target value, updating these piece of information into connection information and delay information of the wirings after changing the wiring connection, calculating a distribution about each wiring path by the analysis based on the post-updating connection information and the post-updating delay information of the wirings and a fluctuation factor, calculating a yield of the integrated circuit from the distribution, and judging whether or not the yield is within an allowable range of a predetermined value.