Patent attributes
A thin film transistor array substrate includes a substrate, scan lines, data lines, thin film transistors, pixel electrodes, common lines and an upper electrode. The scan lines and the data lines are disposed over the substrate to define a plurality of pixel areas. Each thin film transistor is disposed within one of the pixel areas and driven by one of the scan lines and one of the data lines. Each pixel electrode is also disposed within one of the pixel areas and is electrically connected to one of the thin film transistors. The common lines are disposed over the substrate such that a portion area of each pixel electrode is above one of the common lines. The upper electrode is disposed between the pixel electrode and one of the common lines. The upper electrode is electrically connected to the pixel electrode.
