US Patent 7427886 Clock generating method and circuit thereof

A clock generating method and circuit are provided. The circuit includes a basic clock unit, a plurality of subclock units, which are connected in parallel or in series, and a plurality of special control units (SCU). The basic clock unit provides a basic clock signal and each of the clock units provides a corresponding clock signal. Each of the special control units are disposed between two adjacent clock units to delay the clock signal generated by the clock unit connected to the output terminal of the special control units.