US Patent 7428630 Processor adapted to receive different instruction sets

A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1:i+1˜i+4; F2:i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation.