US Patent 7429526 Method of forming silicide gate with interlayer

A field-effect transistor (“FET”) or similar device has a fully silicided (“FUSI”) gate electrode. The gate electrode has a gate interface silicide portion between the gate dielectric and a bulk gate silicide portion. The gate interface silicide is formed by depositing a gate electrode interface layer having silicide retardation species underneath the metal/silicon layers used to form the gate silicide. The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed, and the gate interface silicide is then formed at a higher temperature or longer heat cycle time.