US Patent 7430134 Memory cell structure of SRAM

Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and second write buffer transistors to the latch circuit which stores data and the path is controlled by use of a word line and data write bit lines. Further, a read path is formed by connecting a read driver transistor and read transfer gate to the latch circuit and the path is controlled by use of the word line, read bit line and data of the latch circuit.