US Patent 7432674 Control system

A transmission path delay is set in a shift setting register. A slave unit generates a PRE_ITP signal in response to a timing signal (ITP signal) issued by a master unit. The phase difference between this PRE_ITP signal and the ITP signal unique to the slave unit is loaded into a period modification counter. A timer corrects a reference value, outputs position/speed control period signals (SYN signals) and counts down the period modification counter with these SYN signals until the period modification counter reaches zero. Furthermore, the ITP signal unique to the slave unit is outputted every time a predetermined number of the SYN signals are outputted.