US Patent 7433257 Semiconductor memory device

When a memory cell is inactive, a memory cell power supply voltage control circuit decreases the power supply voltage supplied to the memory cell down to a memory cell holding voltage, thereby reducing the leak current flowing in the memory cell. By reducing the leak current, it is possible to reduce the power consumption of a semiconductor memory device and to increase the operating speed thereof. Moreover, the threshold voltage of transistors in the memory cell is kept low, thereby improving the operating characteristics of the semiconductor memory device at low power supply voltages.