US Patent 7433426 Adaptive hysteresis receiver for a high speed digital signal

An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.