US Patent 7439805 Enhancement-depletion Darlington device

An apparatus comprising a Darlington transistor pair comprising a first transistor and a second transistor. The first transistor may have a gate configured to receive an input signal. The second transistor may have a gate coupled to a source of the first transistor. The Darlington transistor pair may be configured to generate an output signal at a drain of the first transistor and a drain of the second transistor in response to the input signal. The first transistor may be implemented as an enhancement mode device and the second transistor may be implemented as a depletion mode device.