Patent attributes
A signal detector comprises a signal translator, a data signal detector, a clock signal detector and an inputting control circuit for detecting abnormal clock and data signals. The signal translator respectively converts differential data signals and differential clock signal into a single data signal and a single clock signal. The data signal detector outputs a data detecting signal according to the single data signal. The clock signal detector outputs a clock detecting signal according to the single clock signal. The interrupting control circuit receives the data detecting signal and outputs a shutdown signal when the single data signal is at high voltage level over a predefined ratio. The interrupting control circuit also receives the clock detecting signal and outputs the shutdown signal when the single clock signal abnormally disappears.
