Patent attributes
A counter control signal generating circuit is disclosed. The circuit includes a first counter configured to receive a latched external address, and count the latched external address for a first latency, thereby generating a first counted address, a second counter for counting the first counted address for a second latency, thereby generating a second counted address, a counter control signal generator configured to receive a write recognition signal, which is enabled in response to a write command, and generate a counter control signal for controlling enabling of the second counter, in response to the write recognition signal, a first detecting signal generator configured to receive the write recognition signal, generate a first command signal obtained after counting of the write recognition signal for the first latency, and generate a first detecting signal, which is enabled in response to the write recognition signal, and a second detecting signal generator configured to receive the first command signal, generate a second command signal obtained after counting of the first command signal for the second latency, and generate a second detecting signal, which is enabled in response to the first command signal.
