Patent attributes
An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a drain disposed in the well on the both sides of the gate. During an erasing operation, a first voltage is applied to the source of the selected memory cell, a second voltage is applied to the gate of each selected memory cell, and a third voltage is applied to the well; and the drain of the selected memory cell is floated, so that the selected memory cell is erased. In the meantime, the fourth voltage is applied to the drain of each unselected memory cell, the fifth voltage is applied to the gate of the unselected memory cell, and the source of the unselected memory cell is floated to prevent the unselected memory cell from being erased.
