US Patent 7453103 Semiconductor constructions

Patent 7453103 was granted and assigned to Micron Technology on November, 2008 by the United States Patent and Trademark Office.

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Patent Citations Received

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US Patent 11968821 Methods used in fabricating integrated circuitry and methods of forming 2T-1C memory cell arrays

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Patent Inventor Names

H. Montgomery Manning0

Todd R. Abbott0

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Patent abstract

The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.

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Official Website

https://pdfpiw.uspto.gov/.piw?Docid=074531030

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